Circuit Verification Engineer

We are seeking a senior-level verification engineer, with a strong emphasis on analog circuit behavior and timing characterization. In this role, you will drive verification of SRAM/register file memory compilers, mentor junior team members, and elevate our team’s expertise in volatile memory design and verification. Lead end-to-end verification of memory compiler instances, ensuring functional correctness and robust analog circuit performance (sense amplifiers, write drivers, bitline pre-charge, wordline decoders, and critical analog paths). • Execute verification plans for timing requirements – including read/write access times, setup/hold margins, and clock-to-q delays – and validate corresponding .lib files for liberty timing models. • Perform regression management and root-cause analysis of mismatches found. • Guide junior engineers in analog/mixed-signal verification methodologies, and debug workflows; foster a culture of rigorous validation. • Collaborate with circuit designers to any refinement and improvement on memory compiler verification infrastructure.

BSEE/MSEE with 5+ years of experience in memory or custom circuit verification. • Strong analog circuit design knowledge – ability to interpret transistor-level schematics, circuit analysis, transient waveforms, noise margins and etc. • Hands-on experience with memory timing characterization and validation of .lib generation (Liberty format). • Proven track record in memory compiler verification (regression suites, pattern generation, and failure triage). Preferred Experience • Deep understanding of SRAM/register file architectures (6T/8T/10T cells, column mux, redundancy, and assist circuits). • Lead verification planning and execution for multiple compiler variants. • Train and mentor junior engineers, upleveling team competency in analog verification flows and memory-specific debug techniques.