Job Description
● RTL development and integration including RTL coding, RTL checkers, SDC
development, timing report and collaterals generation and synthesis & functional
equivalence checking.
● RTL Coding: Develop high-quality RTL code for digital circuits, adhering to design
specifications, coding standards, and performance requirements.
● RTL-Integration: Integrate the designed IP blocks into larger systems, ensuring
compatibility and proper functionality.
● Linting and CDC: Conduct linting and clock domain crossing (CDC) analysis to identify
and address potential design issues.
● SDC Development: Develop Static Design Constraints (SDC) to define the timing
requirements and constraints for the design.
● Timing Analysis: Perform static timing analysis (STA) to ensure that the design meets
timing constraints and identify potential issues.
● Test and Release: Participate in the testing and release process of the design, ensuring it
meets quality standards and is ready for production.
Requirements
● Bachelor's or Master's degree in Electrical Engineering or Computer Engineering.
● Preferred minimum 4 years of hands-on experience in IP or subsystem hardware design
and integration.
● Proficiency in Verilog/SystemVerilog and familiarity with verification and lint tools (e.g.,
Spyglass, VCS).
● Experience with Clock domain crossing (CDC) & Reset domain crossing (RDC)
● Strong understanding of SoC design flows and integration methodologies.
● Knowledge of timing analysis tools and techniques (Primetime, Tempus)
● Excellent problem-solving, communication, and leadership skills with proven ability to
work across global teams.
Additional Skills:
• Knowledge of power optimization strategies including Power Gating and Clock Gating.
• Experience with embedded processors and interconnect architectures (e.g., NoC).
• Scripting skills in Python or Perl for automation and productivity.
• Knowledge to complete early synthesis and functional equivalence checks